The present invention relates in general to computer aided circuit design tools, and in particular to a circuit simulator capable of performing real-world estimation of signal crosstalk based on forward-annotated inter-signal timing information.
In electronic circuits, crosstalk noise is generated when signal activity on one signal conductor network ("signal net") couples as noise to neighboring signal nets through parasitic capacitances and/or mutual inductances. The amount of crosstalk is essentially a function of circuit layout geometry (proximity of signal nets with respect to each other), circuit characteristics (signal speed and strength), and inter-signal timing (relative timing of signal switching between neighboring nets). To minimize the undesirable effects of crosstalk noise on circuit performance, crosstalk analysis tools have been developed to predict the magnitude of crosstalk. This information is used by the designer to modify the circuit layout and to improve performance by minimizing crosstalk noise.
Existing crosstalk analysis tools comprehend the physical layout geometry of the circuit interconnections to extract trace parasitics. These tools also account for circuit characteristics such as edge speeds for the drivers of the offending neighbor nets. For inter-signal timing information, however, these tools typically make a simplifying assumption that yields a worst case analysis. Typically, the crosstalk calculation tools assume that all signal nets switch at the same time; thereby combining the crosstalk contributions from all of the neighbor nets directly together to produce a crosstalk pulse on the victim net.
The timing of signal transitions on neighbor nets relative to each other is one of the more critical factors in predicting the magnitude of crosstalk noise. This is illustrated by the example in FIG. 1 where four neighboring signal networks SIG1, SIG2, SIG3, and SIG4 couple noise onto the victim signal network SIG0. Each net is connected to a respective driver (D0, D1, D2, D3, and D4) and receiver (R0, R1, R2, R3, and R4). If we assume each of the four neighbor nets generates 100 mV of crosstalk during switching, the worst case assumption yields a total of 400 mV as the magnitude of the crosstalk coupling onto SIG0. This essentially assumes that when a victim net is analyzed, all neighbors switch simultaneously as shown in the timing diagram of FIG. 2A. If signal transitions on the neighbor nets are not in phase, however, then merely adding the crosstalk noise of each net results in an incorrect assumption of the worst case. FIG. 2B shows a more realistic example of signal timing for the four signals. As shown, four independent 100 mV crosstalk pulses are generated at different times, resulting in a total crosstalk value of 100 mV. Therefore an error factor of 300% is made by overly pessimistic timing assumptions. Furthermore, depending on when the receiver on the victim net (R0) samples the signal on SIG0, for example when the clock signal CLK0 is activated, there might be zero crosstalk that affects the receiver (R0) circuitry.
Therefore, even a crosstalk analysis tool with perfect modeling of geometric coupling, without inter-signal timing information, will yield highly exaggerated crosstalk estimations and will falsely predict that many of the signal nets have failed their crosstalk noise threshold. In most high density designs this inaccuracy can quickly grow to an order of magnitude, causing unacceptable numbers of crosstalk false alarms. With the trend toward design of higher speed circuits in smaller packages, the conventional crosstalk analysis tools thus have become effectively obsolete.
One crosstalk analysis tool that has attempted to address this problem is Cadence Design Systems Inc.'s Allegro CBD. Allegro was modified to allow the user to manually input timing information properties. For example, Allegro allows the user to specify properties describing time periods during which individual nets are active (i.e. change states). Allegro will avoid summing crosstalk from two neighbor nets if the signals on those neighbor nets have non-overlapping active periods. This drastically reduces crosstalk pessimism. This approach, however, places a heavy burden on the designer and tends to be tedious and error prone. The user must manually consider, generate and input all the multiple timing modes of design operations and all of the detailed incremental delays beyond the clocking.
From the foregoing, it can be appreciated that there is a need for an improved crosstalk analysis tool capable of calculating crosstalk with real-world timing accuracy.